ADVANS Group in Portugal is looking for experienced Analoc IC Layout Engineers to work in the semiconductor industry in our new Lisbon offices.
Key Responsibilities:
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Design and implement analog IC layouts including floor planning, integration, area estimation, and abstract view generation
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Perform placement and routing at block, top, and full-chip levels in the Cadence Virtuoso environment
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Develop and layout I/O structures, ESD protection, PADs, and seal rings following advanced node constraints
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Execute and debug physical verification checks including DRC, LVS, ERC, and antenna rule checks using industry-standard tools (Assura, PVS, Calibre)
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Conduct parasitic and electromigration (EM) extractions, and collaborate closely with Analog Design Engineers to ensure performance and reliability
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Address and optimize FinFET-specific challenges, including layout-dependent effects (LDE), double-patterning, DFM, and reliability constraints in nodes below 10nm
Qualification Requirements:
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BSc or MSc in in electrical engineering or related field
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5+ years of professional experience in Analog IC Layout, with at least 2 years in FinFET technologies (e.g., 7nm, 5nm, 3nm nodes)
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Hands-on experience with Cadence Virtuoso, Assura, PVS, and/or Mentor Calibre layout and verification tools
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Strong understanding of analog layout principles, ESD/LU protection, parasitic-aware design, DFM, EM, antenna effects, and FinFET-specific LDE
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Comfortable working in a Linux-based CAD environment
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Scripting knowledge (e.g., SKILL, Shell, Perl, TCL) is a plus
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Excellent English communication skills, both written and verbal
Benefits:
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Integration program in a professional, young & dynamic team
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Professional development opportunities
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Competitive salaries & benefits
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Health insurance
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International work environment
